The present invention relates to a semiconductor component arrangements and particularly silicon-on-insulator semiconductor wafers. Semiconductor component arrangements of this type, which are also referred to as SOI components irrespective of the semiconductor material used for the semiconductor layer, are generally known.
In the case of these components, the thickness of the insulation layer arranged between the semiconductor substrate and the semiconductor layer is dimensioned such that, in the case of the maximum potential differences that occur between the substrate, which is usually at a fixed potential, and the potentials occurring in the semiconductor layer, a sufficient dielectric strength is ensured and a voltage breakdown of the insulation layer is prevented. In the case of power components having a dielectric strength in the region of a few kV, the insulation layer must be designed with appropriate thickness. What is disadvantageous in this case, besides the higher production costs, is that the thermal resistance of the insulation layer increases as the thickness increases, thereby impairing the heat dissipation from the semiconductor layer to the semiconductor substrate situated beneath the insulation layer.
In order to improve the heat dissipation from a semiconductor layer which is formed on an insulation layer above a semiconductor substrate and in which symmetrically constructed lateral MOSFETs are formed, it is known from U.S. Pat. No. 6,121,661 to connect the source and drain zones of the MOSFETs to the substrate via heavily doped semiconductor zones through the insulation layer. Said semiconductor zones are of the same conduction type as the source and drain zones and doped complementarily to the substrate. The MOSFETs described in the aforementioned document are logic components, which can be discerned from the absence of a drift zone, and are thus designed for correspondingly low dielectric strengths.
DE 101 06 073 A1 describes the realization of a power component in a semiconductor layer on a thin insulation layer that is suitable for logic components, provision being made, for the purpose of reducing the voltage loading on the insulation layer, for lengthening the terminal zone of the component which has the highest potential with respect to the substrate through the insulation layer right into the complementarily doped substrate.